"Warp processors dynamically optimize their software to improve execution time and energy consumption by performing optimizations at runtime. In addition, Warp processors greatly improve upon previous dynamic optimization approaches, such as BOA and Dynamo. By performing hardware/software partitioning at runtime, warp processors are capable of achieving speedups averaging 7.4 and energy savings up to 94%. In the future, warp processors are expected to achieve speedups much greater than an order of magnitude." (taken from the WARP Processors Homepage)

"The Rotating Instruction Set Processing Platform (RISPP) is a novel processor architecture that combines the paradigms of extensible processor design with the paradigm of dynamic re-confi­gu­ra­tion. Due to its characteristics and adapting properties it is able to address the following concerns in embedded processing:

• an application might have many computational hot spots that would require a large additional chip area in order to comprise all beneficial customizations
• the characteristics of an application may widely vary during run-time due to switching between different operation modes, changing constraints (e.g. if the systems runs out of energy), or highly in-correlated input stimuli patterns."

(taken from the RISPP homepage)

"JHDL is a set of FPGA CAD tools developed at Brigham Young University's Configurable Computing Laboratory that allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist and interface for bit-stream synthesis, and so forth. It is an exploratory attempt to identify the key features and functionality of good FPGA tools." (taken from the JHDL Homepage)

"This project addresses hardware and forware-compatibility limitations by virtualizing hardware, which allows a hardware design of any size to execute on a compatible device with any capacity. Hardware virtualization is accomplished through extremely high-speed reconfiguration. PipeRench provides the high-speed reconfiguration necessary for hardware virtualization, compilation tools for this architecture, and applications that will demonstrate both high-performance and forward-compatibility." (taken from the PipeRench Homepage)

"The goal of the research is to bridge the gap between traditional processors and application-specific hardware solutions to replace many of the ASIC and DSP components with a configurable hardware solution that retains much of the advantages of ASICs but with the flexibility of programmable processors. The approach is to blend ideas from configurable hardware systems and processor architectures to create scalable VLIW-based architectures for embedded computations." (taken from the RaPiD Homepage)

"The focus of the Garp research is the integration of a reconfigurable computing unit with an ordinary RISC processor to form a single combined processor chip. The goal of the research is to demonstrate a tentative viable architecture that gives a speedup for at least some applications." (taken from the GARP Homepage)

The Grid Alu Processor (GAP) is a runtime reconfigurable processor designed for the acceleration of a conventional sequential instruction stream without the need of recompilation. It comprises a superscalar processor front-end, a novel configuration unit, and an array of reconfigurable functional units (FUs), which is fully integrated into the pipeline. The configuration unit maps data dependent and independent instructions simultaneously at run-time into the array of FUs. The dynamic mapping allows the acceleration of sequential control-flow-oriented applications. Moreover, the execution of loop iterations is accelerated by executing the loop inside the array of FUs. (taken from the GAP homepage)